Danishazmi29/Verilog-Code-of-Synchronus-FIFO-Design-with-verilog-test-code ? reverse-engineered prompt

Build me a simple synchronous FIFO in Verilog, with a matching testbench so I can simulate it and see it working.

I want it to behave like a normal queue in hardware, with separate read and write pointers, a small memory array, and clear full and empty flags. Please make it easy to understand and keep the code clean, since this is for learning how FIFO storage works between two parts of a circuit. If you can, include a basic output log from the simulation so I can confirm the reads and writes are happening in the right order.

Please also make sure the testbench checks the main cases, like writing data in, reading it back out, and what happens when the FIFO is full or empty. If anything is unclear, look up the current Verilog simulation syntax online and use a straightforward approach that will run in a common simulator.