Essenceia/Nasdaq-HFT-FPGA — reverse-engineered prompt

Build me an FPGA RTL project for a very low latency Nasdaq market data interface. It should receive UDP multicast Ethernet traffic, handle MoldUDP64 packets on an AXI stream, detect missing messages, and decode TotalView ITCH 5.0 including Glimpse messages into clean signals that other trading logic could use.

Include the Ethernet pieces needed for 10G and 40G style links, MAC, IPv4, UDP, and TCP if needed, but keep the first working goal focused on receive and decode. Add a top level module and a simulation testbench that can read a Nasdaq ITCH binary dump, wrap it as MoldUDP64, stream it into the design, and compare the decoded output.

I want simple make commands to run the simulation with iverilog, plus an option to dump waves for gtkwave. Please keep the code organized and documented enough that I can follow it, and look up current docs online if you need to.