JaydevArapada-26/risc-v-32bit-core ? reverse-engineered prompt

Build me a small Verilog project for a 32 bit RISC V single cycle processor that can run a basic RV32I subset. I want the core datapath split into clear modules like the ALU, control unit, ALU decode logic, register file, instruction memory, immediate generator, and a top level CPU that ties everything together.

It should support simple arithmetic and logic instructions like ADD, SUB, AND, OR, XOR, plus ADDI, and x0 should always stay zero. Please include testbenches for the main modules and the full CPU, and make them easy to run with Icarus Verilog. I’d also like a sample program hex file and waveforms dumped to VCD so I can inspect the simulation in GTKWave.

If you need to check any current Verilog or RISC V details online while building it, feel free to look them up.