LSFF-23/relay-core — reverse-engineered prompt

I want a simple FPGA style protection relay core in SystemVerilog that feels complete enough to simulate and understand without a lot of extra setup.

Please wire the existing modules into a clean top level design that takes in sampled voltage data, does the basic signal processing needed to estimate magnitude or RMS, and raises a trip output for an ANSI 59 style overvoltage condition. If the code already points in that direction, keep that intent and finish the missing pieces instead of reinventing it.

Make it easy to run by adding a small testbench that feeds in normal and fault cases so I can see the relay stay idle, then assert trip when the voltage goes over the limit for the right amount of time. I would also like short comments and a brief usage note explaining what each main module does, what the key inputs and outputs are, and how to change the threshold or timing settings. If anything is unclear, look up current docs online if you need to.