MohamedHussein27/FIFO-UVM ? reverse-engineered prompt

Build me a complete SystemVerilog verification project for a synchronous FIFO using UVM.

I want the FIFO design and the full testbench set up so I can run simulations and verify normal reads and writes, reset behavior, full and empty conditions, almost full and almost empty flags, plus overflow and underflow cases. Please include a clean UVM environment with an interface, transaction, sequencer, driver, monitor, scoreboard, coverage collector, assertions, and a top level testbench that connects everything together.

Make the FIFO configurable for data width and depth, and handle the case where read and write happen together in a sensible way, with write taking priority when the FIFO is not full and read when it is not empty. Add a few useful sequences like write only, read only, mixed read write, and reset during operation. If anything is unclear, follow common UVM practice and look up current docs online if you need to. I’d like it organized so it’s easy to simulate and understand.