TinyTapeout/ttihp-verilog-template ? reverse-engineered prompt

Build me a Tiny Tapeout Verilog project template that I can use to submit a simple digital design to an IHP shuttle.

I want the repo set up so I can drop my Verilog into the src folder, update the project details in info.yaml, and write a short description in docs/info.md. Please make sure the testbench is easy to adapt for whatever top module I choose, and that the project is ready to run the normal checks for simulation, FPGA, docs, and GDS generation.

Keep it beginner friendly and aligned with Tiny Tapeout’s workflow, since this is meant to help someone get from an idea to a chip submission without a lot of extra setup. If anything is unclear from the current files, look up the latest Tiny Tapeout docs online and follow their current expectations.