Ujwal123434/100-days-of-rtl ? reverse-engineered prompt

Build me a Verilog RTL practice project called 100 Days RTL Design Challenge.

I want it to feel like a real learning repo where each day has one small digital design problem, like sequence detectors, a synchronous FIFO, a priority encoder, a UART transmitter, a LIFO, and an edge detector. Please set it up so each design is in its own folder with clear Verilog code and simple testbenches that I can run in Icarus Verilog or Vivado.

The main goal is to make it easy to study, simulate, and learn from each module, so keep the code clean and beginner friendly, with comments where they help. If you need to look up current Verilog or simulator details online, go ahead. I also want the project to look good as a portfolio piece, so make the README helpful and keep the examples focused on RTL design concepts and interview prep.