Ujwal123434/Verilog-Projects ? reverse-engineered prompt

Build me a small Verilog project with two parts, a UART and a synchronous FIFO, and make it easy to simulate in Vivado.

For the UART, I want an 8 bit transmitter and receiver with a baud rate generator, start and stop bit handling, and simple handshake signals so I can start a send, know when it is busy, and read received data when it is done. Use inputs like clock, reset, transmit start, transmit data, and receive line, and give me transmit output, received data, done, and busy signals.

For the FIFO, make a parameterized synchronous FIFO that works on one clock, with configurable depth and data width, plus read and write control, full and empty flags, and circular pointer logic.

Please include clean Verilog code and self checking testbenches for both parts, so I can run simulations and see that they work. If anything is unclear, use common practical defaults and look up current Vivado friendly Verilog style if you need to.