Ujwal123434/verilog ? reverse-engineered prompt

Build me a clean Verilog learning project for basic digital circuits, with both the design modules and matching testbenches so I can run simulations and see the results clearly.

I want the common building blocks covered, like basic gates, adders, subtractor, mux and demux, encoder and decoder, comparator, latches and flip flops, and a few counters. Keep everything synthesizable and organized in separate folders so it is easy to follow. For each circuit, add a simple testbench that tries a few different input cases and shows the expected behavior in simulation.

Please also add short README notes for each section so someone new to Verilog can understand what each circuit does and how to simulate it in Vivado. If anything needs current tool guidance, look up the latest docs online. Make the code readable and consistent across all the examples, and include enough examples that this can work as a small educational portfolio.