YosysHQ/picorv32 — reverse-engineered prompt

Build me a small RISC V CPU core in Verilog that I can drop into an FPGA or ASIC project as an auxiliary processor. I want it to focus on being tiny but still fast, with configurable options so I can choose a minimal RV32E or RV32I setup, or enable compressed instructions, multiply and divide support, counters, interrupts, and a simple coprocessor interface.

Please include the main CPU core, plus versions that can talk over a simple native memory interface, AXI4 Lite, and Wishbone. Add clear parameters so I can trade off size and speed, like smaller register files or optional instruction support.

I also want a basic test setup with simple firmware, instruction tests, an easy testbench that works without a RISC V compiler, and examples showing how to run a tiny SoC from memory mapped SPI flash. Include a Makefile and enough README documentation that I can simulate it and know how to integrate it.