aachcoder47/VLSI-AGENT ? reverse-engineered prompt

Build me a web app for hardware engineers that helps with RTL verification and debugging in one place.

I want a clean dashboard where I can paste or upload Verilog or SystemVerilog code, run checks for common issues like latch inference, blocking assignment problems, and unused signals, and see the results highlighted right in the editor. It should also let me upload a VCD waveform file, show the signals over time in a simple visual viewer, and help me jump from an assertion failure time back to the likely source line. Include a way to generate a basic testbench and SystemVerilog assertions from the design.

Also add a section for synthesis and timing summaries, like rough area, flip flop counts, and slack estimates, plus a research helper that can answer questions from IEEE style documentation if needed. Make it feel like a modern AI assistant for chip design, with a multi agent style workflow and a polished frontend I can use locally at localhost. If you need current docs for the tools, look them up online.