aanchaljain07/AMBA_APB-UVM-Verification ? reverse-engineered prompt

Build me a SystemVerilog UVM verification project for an APB bus DUT, with a clean reusable testbench that can run read, write, mixed read write, reset, and basic error checks.

I want the usual UVM pieces wired together, sequence item, sequence, sequencer, driver, monitor, agent, scoreboard, coverage collector, environment, test, and top level. Please include an APB interface, a simple RTL design to verify, and a simulation setup that can be run from the makefile. The testbench should drive APB through the normal idle, setup, and access phases, check transactions against the scoreboard, and collect coverage for the main cases.

Please keep the code organized so it is easy to understand and reuse, and make sure the log output clearly shows when write and read transactions happen and whether they passed. If anything important is missing, add sensible defaults so the whole project can run end to end.