himansh107/nitjsr_pll_130nm — reverse-engineered prompt

Build me an open source 130 nm clock multiplier PLL project using the Sky130 PDK and common free EDA tools. I want the PLL to take a low frequency reference clock and generate an output clock that is 8 times faster, with clear pre layout and post layout simulation results.

Please include the main PLL blocks, phase frequency detector, charge pump, loop filter, voltage controlled oscillator, and feedback divider. Make the project easy to understand for someone reviewing it, with a clean README that explains what a PLL does, why it is useful, the block diagram, design choices, and the expected behavior of each block.

I also want simulation screenshots or plots for the individual blocks and the full PLL, plus tables showing supply voltage, reference frequency, output frequency, control voltage, duty cycle, and settling time before and after layout. Use xschem, ngspice, magic, and Sky130 conventions. Look up current tool docs online if needed.