hyliu1989/SLM_FPGA ? reverse-engineered prompt

Build me the FPGA project for controlling an SLM on the DE1 SoC board.

I want it to handle VGA style sync signals correctly, write test image data into a FIFO, load vertical strip patterns into memory, and move data from memory to the FIFO based on the selected line and image. It should also support JTAG UART so I can download images from the PC into the board memory and send simple experimental commands, with some easy visual feedback like the seven segment displays showing when loading is happening.

Please make it work as a complete Quartus project I can compile and program onto the DE1 SoC, including the Qsys system and the top level Verilog. If anything needs a current tool setting or reference, look up the latest docs online if needed.