juheon727/logic2026f_study ? reverse-engineered prompt

Build me a Verilog study repo for a digital logic course, organized by chapter, with working source files and simple testbenches for the main lab exercises.

I want examples for hazard analysis, basic combinational logic, adders and carry lookahead, latches and flip flops, an 8 bit ALU, a register file, stack logic, resettable flip flops, a pulse generator, a shift register, and a serial adder. Please include simulation friendly testbenches that can generate VCD waveform files, and make the modules easy to run with iverilog and inspect with yosys if needed. Keep the code clean and educational, with separate files for the design and the testbench where that makes sense.

If anything is ambiguous, use standard digital logic behavior and look up current Verilog or simulation details online if you need to.