krss-94/fpga-masked-share-routing ? reverse-engineered prompt

Build me a small research tool that helps check whether two masked shares on a Xilinx FPGA stay physically separated after place and route.

I want it to take a design, run through the FPGA build flow, then scan the routed nets and flag any places where the two shares end up sharing the same switch box or tile path. It should also try a few ways to fix the problem with routing or constraints, then rerun the build and report whether the conflicts went away or not.

Please include clear outputs like a conflict summary, how many issues were found, what got fixed, what could not be fixed, and simple visual reports if possible. If there are scripts or docs needed to reproduce the flow, set those up too. If you need to check current Vivado or RapidWright docs online, go ahead.