krss-94/riscv-fusion-isolation-pipeline ? reverse-engineered prompt

Build me a small RISC V CPU project in SystemVerilog, starting from a simple 5 stage in order RV32IM pipeline. I want it to support a basic instruction fusion feature in decode, plus a hardware isolation gate around the multiply divide unit, with the usual hazard, forwarding, stall, and clear logic working correctly.

Please include a test setup that can run against Spike for cycle accurate checking, plus the official RISC V compliance programs and a few benchmark style runs so I can tell it is behaving right. I’d also like the project organized so I can build and compare a baseline version, a fusion only version, an isolation only version, and a combined version. If you can, add the scripts needed for Vivado synthesis and timing or power checks too, and make sure the code is readable enough that I can tweak the fusion and isolation behavior later.