kubeworkz/grx930 ? reverse-engineered prompt

Build me this GRX930 RISC V AI SoC project from scratch, with the same overall idea as the README. I want a working SystemVerilog design for a small multi core RISC V system with caches, an AXI4 bus, a simple UART, interrupt controller, boot ROM, and a memory stub that can run on an FPGA. It should also include the NPU with the 8 by 8 matrix multiply blocks and the basic CSR and DMA hookup so firmware can talk to it.

Please make sure the design can be simulated and that there are testbenches for the main pieces, including the CPU side, the arbiter, the cache, and the NPU paths. If possible, add the Vivado flow and constraints for the Nexys Video board so it can be built for the target FPGA too. Look up current docs online if you need to, and keep the code organized so I can run the sim and synth flows without a lot of manual setup.