luanbalbino/AXI_UVM ? reverse-engineered prompt

Build me a simple SystemVerilog project for studying AXI4 Lite, with an AXI4 Lite slave connected to a tiny processing FSM core, plus a UVM testbench around it.

I want the slave to support the normal read and write handshakes, backpressure on the address and data channels, byte enables with WSTRB, and proper OKAY and SLVERR responses for valid and invalid accesses. Use a small register map with CTRL, STATUS, DATA or RESULT, and CONFIG, where writing CTRL starts the core, CONFIG controls a latency and shift amount, and reading DATA returns the computed result after the core finishes.

Also build the verification environment so I can run directed tests and some random tests for writes, reads, partial writes, invalid addresses, and randomized READY behavior. Include a scoreboard that checks the register behavior and responses, and make it easy to run waveforms and debug the transactions. If you need current UVM or SystemVerilog syntax details, look them up online first.