prajwalgekkouga/AHB-to-APB-Bridge — reverse-engineered prompt

Build me a simple Verilog AHB to APB bridge project that I can simulate. I want an AHB master to send one write and one read request, and the bridge should convert those into the correct APB style transfers for a selected peripheral.

Please make the bridge synthesizable and easy to follow. It should latch the AHB address, decode it into a peripheral select signal, pass write data to APB, return read data back to AHB, and generate the APB timing signals like PSEL, PENABLE, PWRITE, PADDR, PWDATA, and PRDATA. Include a clear top module that connects the AHB slave side, APB controller, APB interface, and a simple test setup.

Also add a testbench that proves the single write and single read work correctly, with useful simulation messages and wave signals. Keep it compatible with ModelSim, and make the code clean enough that it could later be opened in Quartus for a Cyclone V FPGA. Look up AMBA timing details online if needed.