rafaelcalcada/rvx ? reverse-engineered prompt

Build me a small RISC V microcontroller core in Verilog called RVX that can be dropped into FPGA projects and also used as IP for embedded work. It should implement RV32I and include the basic things a simple microcontroller needs like memory, timers, UART, GPIO, and SPI, so it can run bare metal code and a FreeRTOS demo.

Please make the project feel complete, with a clear top level design, a simple way to run the included examples, and enough documentation so someone can get started without guessing. I want a Hello World example that shows the core working, plus a FreeRTOS example for a more realistic setup. If you need to check current docs or best practices for RV32I or common FPGA flows, feel free to look them up online.

Keep it practical and easy to integrate, with readable code and sensible defaults.