samsajwani1234/CA-Lab-Project ? reverse-engineered prompt

I want you to help me finish this computer architecture lab project in Verilog.

There are three task folders, so please inspect each one and build out whatever modules, testbenches, and top level code are needed so the tasks work properly. Keep the code simple, clear, and educational, like something a student could submit for a lab. If anything is missing or unclear, infer the most likely setup from the existing files and the report.

Please make sure each task can be simulated easily, and organize the project so it is straightforward to run and understand. If you need to, look up current Verilog syntax or simulation details online, but keep the solution focused on the lab requirements. I’d also like a brief explanation of what each task is doing, so I can study from it and present it confidently.