sarthak268/Embedded_Logic_and_Design — reverse-engineered prompt

Build me a clean Embedded Logic and Design lab repository in Verilog that I can open and use for course submissions in Vivado.

I want separate lab folders with working designs for the basics like half adder, full adder, 4 bit adder and subtractor, Boolean expression implementations, counters on ZedBoard, binary to BCD conversion, seven segment display output, BCD adder, SIPO shift register, and FSM sequence detectors for Moore and Mealy machines. Also include the later board based work, like keypad input through PMOD on Basys 3, simple GPIO based ARM Cortex A9 designs for ZedBoard or Zybo, and an interrupt design where push buttons change the number shown on the seven segment display.

Please add simple testbenches where it makes sense, clear module names, and short README notes for each lab explaining what the design does, what inputs and outputs to use, and how to verify it on the board. Look up Vivado or board docs online if you need to.