suganthan7755/RTL-Design-and-Verification-Projects ? reverse-engineered prompt

Build me a complete SystemVerilog project for verifying an IEEE 754 floating point high speed parallel multiplier.

I want a clean RTL plus verification setup with a UVM testbench, basic assertions, and functional coverage so I can run directed and random tests and see that the multiplier works correctly for normal values, zeros, infinities, NaNs, and edge cases like overflow and underflow. Please include a simple top level testbench, the transaction and sequence classes, driver, monitor, scoreboard, and a few useful test cases. Add comments so I can understand what each piece is doing, and make the project easy to compile and run in a simulator.

If you need to check current UVM or SystemVerilog best practices, look up the latest docs online.