vidhyamadhavivemuri-spec/8-bit-RISC-Processor-Design-using-Verilog ? reverse-engineered prompt

Build me a simple 8 bit RISC processor in Verilog, meant for learning and simulation.

I want the full CPU datapath with a program counter, instruction memory, instruction decode and control, an 8 register register file, an 8 bit ALU, data memory, and write back logic. Use a 16 bit instruction format with register and immediate instructions, and include basic ops like add, sub, and, or, xor, mov immediate, load, and store. Please also make the ALU produce a zero flag.

Include clean testbenches for the main modules and for the top level CPU. The top test should run a small program like loading a few values, doing arithmetic and logic operations, then checking the register outputs to make sure everything works. I also want the simulation to generate a VCD file so I can inspect the waveform in GTKWave. If needed, look up current docs online for Icarus Verilog or GTKWave setup details.